1. Field of the Invention
The present invention relates to a frame phase or sampling time estimation method and circuit for use in digital data transmission. Such a circuit is used to estimate the signal phase for a received digital data signal which has been transmitted over a channel subject to multipath delay and containing noise.
2. Description of the Prior Art
If it is given that a sampling point in time for an n.sup.th symbol in a symbol sequence f(n) is represented as t(n), t(n) may be expressed as: EQU t(n)=n.multidot.T+t.sub.0 ( 1)
n: integer PA1 T: symbol period PA1 t.sub.0 : initial value (phase). PA1 k: integer PA1 l: integer, 0&lt;l&lt;.alpha.-1 PA1 .tau..sub.0 : constant determined by the sampling interval.
If oversampling is carried out, that is, the sequence is sampled at .alpha. times the sampling period T, the initial value t.sub.0 is represented by the following equation: EQU t.sub.0 =k.multidot.T+l.multidot.(T/.alpha.)+.tau..sub.0 ( 2)
Thus, in order for the n.sup.th symbol to be correctly sampled at a receiver which receives the symbol sequence x(n) as a received signal r(t), it is necessary to correctly determine the values of k and l, in order to correctly calculate the initial phase value t.sub.0.
If the received signal r(t) is sampled at the receiver with a sampling interval of t(n) where t.sub.0 =k.sub.x .multidot.T+l.sub.x' (T/.alpha.) +.tau..sub.0, the n.sup.th symbol is expressed as r(n; k.sub.x, l.sub.x), where x denotes a variable value of k and l. To determine the correct values of k.sub.x and l.sub.x, a frame synchronization transmission is carried out at the beginning of communication wherein a known transmitted symbol sequence x(n), n=0, 1, . . . , N-1 is transmitted, and a cross-correlation P(k.sub.x, l.sub.x) between the received symbol sequence r(n; k.sub.x, l.sub.x) and the known symbol sequence x(n) is calculated for a predetermined number M of combinations of values of k.sub.x and l.sub.x, wherein ##EQU1##
FIG. 1 is a flow chart showing a frame phase estimation method which is shown in Giovanna D'Aria, Valerio Zingrelli, "Design and performance of synchronization techniques and Viterbi adaptive equalizer for narrow band TDMA mobile radio," Proc. 3rd, NS on DLMRC., pp. 279 to 286, Sept. 1988; in this method, oversampling is not assumed for simplicity and thus the value l is ignored. In the figure, "Initial setting of K" is a step in which an initial setting of an initial signal phase K of a received digital signal is made (an initial value K is set) and the transmitted signal is sampled according to the initial phase; "K=K+ 1" is a step in which the initial phase is changed by adding a delay time equivalent to a period of one sample; "calculation of .vertline.P (K).vertline." is a step in which the cross-correlation between a received digital signal and a known transmitted pattern such as a frame synchronization bit pattern is calculated and the magnitude of the cross-correlation is obtained in the case where the initial phase is decided to be K; and "the storage of Kmax" is a step in which the value of K when the magnitude of the cross-correlation P (K) takes a maximum value is stored.
Next, the explanation of operation will be given.
In a conventional frame phase estimation method, during a frame synchronization period, the initial phase K of a received signal is changed for each processing loop by the addition of a delay time equivalent to a period of one sample of a received signal and an optimum frame phase is estimated as described in the following. At first, the cross-correlation between a received signal corresponding to a given K and a known transmitted pattern is calculated to obtain the magnitude of the cross-correlation. Next, the magnitude .vertline.P (K).vertline. is compared with a magnitude .vertline.P Kmax.vertline. which has been previously stored and if .vertline.P (K).vertline. is larger than .vertline.P Kmax.vertline., K is stored as Kmax and .vertline.P (K).vertline. is stored as .vertline.P (Kmax).vertline., and if .vertline.P (K).vertline. is not larger than .vertline.P (Kmax).vertline., the stored Kmax and .vertline.P (Kmax).vertline. are left as they are. The operation is repeated until K becomes larger than K.sub.0 (a constant determined according to the sampling period), and the final Kmax is regarded as a frame phase estimation value.
FIG. 2 is a block diagram showing a conventional frame phase estimation circuit for realizing the frame phase estimation method described above. In the figure, 11 is a first delay circuit which applies a fixed delay (for example, a value k estimated to be a true fram phase) to a received signal inputted from a received signal input terminal 9; 12 is a second delay circuit which applies a different delay (for example, k+1) from that of the first delay circuit 11 to the received signal circuit 11; 1n is an nth delay circuit which applies a delay (for example, k+(n-1)) different from the first delay circuit 11 and the second delay circuit 12; 21 is a first cross-correlation circuit for calculating the cross-correlation between the output of the first delay circuit 11 and a known pattern of the transmitted signal from a pattern input terminal 10; 22 is a second cross-correlation circuit for calculating the cross-correlation between the output of the second delay circuit 12 and the above-mentioned known signal pattern; 2n is an nth cross-correlation circuit for calculating the cross-correlation between the output of the nth delay circuit 1n and the above-mentioned signal pattern; 8 is a maximum value selection circuit in which a maximum value among the n values of cross-correlations outputted from the cross-correlation circuits 21 to 2n is obtained, and which outputs a delay value corresponding to the obtained maximum value as a frame phase from a frame phase output terminal 30.
Next, the explanation of operation will be given. The first delay circuit 11 applies a fixed delay, previously selected, to a received signal inputted from received signal input terminal 9; the second delay circuit 12 applies a different delay from that of the first delay circuit 11; the nth delay circuit 1n applies a delay different from the delays of the first delay circuit 11 and the second delay circuit 12; in this way, n different values of delays are applied to the received signal. The first cross-correlation circuit 21 calculates the cross-correlation between a delay signal outputted from the first delay circuit 11 and a signal pattern inputted from a pattern input terminal 10; the second cross-correlation circuit 22, in a similar way to the above, calculates the cross-correlation between a delay signal output from the second delay circuit 12 and the signal pattern; the nth cross correlation circuit 2n, in a similar way to the above, calculates the cross-correlation between a delay signal output from the nth delay circuit and the signal pattern; in this way, the values of cross-correlations for n different values of delays are formed. The maximum value selection circuit 8 selects a maximum value among the n values of cross-correlations outputted from the first cross-correlation circuit 21 to the nth cross-correlation circuit 2n, and outputs a delay value corresponding to the maximum value as a frame phase from the frame phase output terminal 30.
FIG. 2A is a block diagram of a conventional frame phase estimation circuit taking into account the value l when oversampling is performed on the received signal r(t). The received signal r(t) is applied to input terminal 42 of sample and hold circuit 43, where it is sampled and stored. M different values of combinations of k.sub.x and l.sub.x are set into the sample and hold circuit 43 by setting circuit 44, in order to set different values for the initial phase t.sub.0. Then, each sampled sequence is inputted into a corresponding cross-correlation circuit 1 to M, where the cross-correlation between the sampled sequence and the known sequence x(n) is calculated, and their absolute values obtained. The results are inputted to maximum cross-correlation selector circuit 8a, where the values of k.sub.x and l.sub.x corresponding to the maximum cross-correlation value are outputted as k.sub.max and l.sub.max to be used in the calculation of t.sub.0 for setting the sampling interval initial phase.
Since the conventional frame phase estimation method and the frame phase estimation circuit are constituted as described above, in the cases where a delayed wave which is generated by multipath propagation delays or the like grows larger than the main wave, or the cross-correlation magnitude is made large by noise etc., there is a problem that a frame phase can be estimated erroneously.
In FIG. 3, examples of magnitudes of cross-correlations corresponding to various initial signal phases, that is, the magnitudes of cross-correlations corresponding to various delay values are shown. In the figure, (1) to (9) show initial signal phases, that is, delay values. In this example, the magnitude of a cross-correlation corresponding to initial phase (6) is the largest and the initial phase (6) is thus estimated to be the true frame phase. In the cases, however, where the cross-correlation magnitude corresponding to an initial phase (8) is made larger (by a delayed wave generated by multi-path propagation delay or interference between signals) than the cross-correlation magnitude generated by the main wave (the cross-correlation corresponding to the initial phase (6)), or where a cross-correlation exists which is made large by noise etc. such as the cross-correlation magnitude shown with a broken line in the initial phase (3), a frame phase can be estimated erroneously.
A digital pulse compressor described in U.S. Pat. No. 4,679,210 is intended for high speed operation of a single correlation value by digitizing a single signal and taking correlation for each of the bits; the frame phase estimation according to the present invention is for calculating a plurality of correlation values having a plurality of bits, and it is different in principle form the invention described in the above mentioned patent.